The present disclosure herein relates to a gate driving circuit and a display device including the same.
A display device includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the plurality of gate lines and the plurality of data lines. The display device includes a gate driving circuit for sequentially providing gate signals to the plurality of gate lines and a data driving circuit for outputting data signals to the plurality of data lines.
The gate driving circuit includes a shift register with a plurality of driving circuits (hereinafter referred to as driving stages). The plurality of driving stages respectively output gate signals corresponding to the plurality of gate lines. Each of the plurality of driving stages includes a plurality of transistors.
When frequencies of gate signals outputted from the gate driving circuit are the same, as the resolution of the display device increases, a time for charging each pixel with electric charges decreases. Pixel charging time reduction may cause the quality of a display image to deteriorate.